In the case of a semiconductor memory module, a module board includes a plurality of semiconductor memory components which communicate with the memory module's environment via a control component. FIG. 1 shows a module board MP on which a control component SB is arranged. The control component SB is situated at a central position on a top of the module board. On left-hand and right-hand sides of the control component, semiconductor memory components HB are arranged on the top of the module board and further semiconductor memory components HB arranged on the bottom of the module board. The semiconductor memory components are connected to the control component via various buses for transmitting clock, control, address and data signals. To this end, the control component comprises a number of clock, control, address and data terminals.
Each of the semiconductor memory components HB includes one or more memory chips C. FIG. 2A shows a semiconductor memory component HB in which four memory chips C are situated in a stack arrangement. Each of the memory chips comprises a memory cell array containing a multiplicity of memory cells. FIG. 2B shows a memory chip comprising a memory cell array in an enlarged illustration. The memory cells are arranged along word lines WL for activating one of the memory cells and bit lines BL for writing a memory state to one of the memory cells or for reading a memory state from one of the memory cells.
In the case of DRAM (Dynamic Random Access Memory) memory cells, a memory cell comprises a selection transistor AT and a storage capacitor SC. The storage capacitor SC can be conductively connected to the bit line BL via an appropriate control signal on the word line WL for the purpose of memory access. To improve the signal integrity for write access, a terminating resistor (On-Die Termination Resistor) ODTW, which is used to terminate a data bus for transmitting the data from the memory chip, is activated on the memory chip.
To activate the terminating resistor, the control component SB actuates the relevant semiconductor memory component or the memory chip of the memory component via a control signal ODTS (On-Die Termination Signal). In addition, the semiconductor memory components are actuated in order to select one of the memory chips of the memory component via a control signal CS (Chip Select Signal). Address signals are produced on address terminals of the control component SB and are supplied to the memory chips via address buses in order to select one of the memory cells in the memory cell array for memory access.
In the case of a memory module with the module configuration 2Rx4, a semiconductor memory module holds a total of 36 memory chips. A rank indicates the number of memory components necessary to provide the bus width for the control component. Since the bus width generally comprises 72 bits, an x4 organizational form for the semiconductor memory comprises 18 memory chips associated with a rank. If the semiconductor memory module in FIG. 1 is operated in a configuration of 2Rx4, each of the semiconductor memory components comprises two memory chips, therefore a total of 36 memory chips are situated on the module board.
Since particularly the control components SB have a high power consumption, great efforts are made to reduce the number of semiconductor memory modules required for implementing a memory with a certain capacity. With a semiconductor memory module in the 4Rx4 module configuration comprising semiconductor memory components that each include two stacked memory chips with a storage density of 1 Gbit, a storage capacity of 8 GB can be produced, for example, while only a storage capacity of 4 GB can be achieved with a semiconductor memory module in the module configuration 2Rx4, which contains semiconductor memory components that each include two stacked memory chips with a storage density of 1 Gbit. Therefore, the power consumption in a memory can be reduced by approximately half if, instead of using memory modules in the 2Rx4 configuration, memory modules in the 4Rx4 configuration are used. In this case, only 8 memory modules in the 4Rx4 configuration are required to design a memory with a storage capacity of 64 GB, for example, whereas 16 semiconductor memory modules in the configuration 2Rx4 would be necessary to design a memory of this kind. Since the number of control components is thus also reduced by half, the use of 8 semiconductor memory modules in the 4Rx4 configuration also allows the power consumption to be reduced by half in comparison with the use of 16 memory modules in the 2Rx4 module configuration.
If the semiconductor memory module in FIG. 1 is designed in a module configuration of 4Rx4, the module board holds a total of 72 memory chips. As FIG. 2A shows, each of the semiconductor memory components respectively contains 4 memory chips in a stack arrangement. To control a semiconductor memory module of this kind, further control signals need to be produced by the control component SB in comparison with a semiconductor memory module in the 2Rx4 configuration. Thus, particularly for the purpose of actuating the two additional ranks, further control signals CS (Chip Select) are required for selecting the memory chips in the additional ranks and additional control signals ODTS are required for activating the terminating resistors for the memory chips in the additional ranks. However, the provision of additional output terminals for providing the additional control signals is associated with an increase in the chip size for the control component and with an increase in the power requirement for the control component.